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Tier-1 brand and Bengaluru metro boost competition, while seniority and niche verification skills moderate density.
Highly domain-specific semiconductor verification skills limit cross-industry transferability.
Explicit 12+ years requirement plus mandatory UVM/RTL and analog expertise enforces strict filters.
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Own the definition and execution of verification plans, methodologies, and coverage strategies for complex SoC designs, including block, subsystem, and full-chip levels.
Architect and implement verification environments and frameworks, integrating VIPs and developing testbench components like agents, scoreboards, and drivers.
Lead end-to-end verification activities including gate level simulation, coverage closure, regression, failure triage, and provide mentorship to junior engineers.
Bachelor's degree in Electrical Engineering or equivalent practical experience.
Minimum 12 years of experience in design verification with strong expertise in UVM, SystemVerilog, Verilog, and relevant simulation and revision control tools.
Proven ability to architect and manage the full verification lifecycle for SoC and mixed-signal designs.
Experience with scripting languages such as Perl and Python for automation and analysis; knowledge of analog components like ADC, DAC, PLL, Oscillators, and PI controllers.
Experienced in complex SoC verification environments with a strong background in mixed-signal and power management solutions.
Technical leader capable of driving verification strategy, mentoring teams, and interfacing with cross-functional groups for RTL and gate level debugging.
Demonstrates advanced problem-solving, logical thinking and analytical skills with a track record of delivering high-quality verification sign-off on automotive or industrial semiconductor products.