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Tier-1 employer and metro location but niche EDA/verification infra specialization limits applicant pool.
Role requires deep hardware verification and EDA infrastructure expertise, limiting cross-industry transferability.
Explicit senior years requirement and specialized EDA, CI/CD, and tool mandates create strict shortlisting filters.
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Maintain and enhance CI/CD infrastructure for CPU design and verification workflows.
Collaborate with RTL, DV, and DFT teams to optimize verification flows and drive automation.
Work with global teams and EDA tool vendors to ensure scalable infrastructure and resolve tool-related issues.
8+ years of work experience in hardware engineering or related roles as per educational qualifications.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years experience, OR Master's with 5+ years, OR PhD with 4+ years.
Strong hands-on experience with Git, GitHub, Python, Shell scripting, LSF, Jenkins, and Airflow.
Not explicitly mentioned: Notice period or strict location requirements.
Experienced in CPU design and verification infrastructure with deep understanding of CI/CD principles.
Skilled in cross-team collaboration across geographies and working with EDA tools and vendors.
Familiarity with RTL design (Verilog/SystemVerilog) and CPU microarchitecture concepts preferred.