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Senior, niche semiconductor DV role reduces applicant density despite Marvell brand, producing moderate competition.
Specialized semiconductor DV skills (UVM, SoC, IP verification) are not easily transferable across industries.
Many mandatory technologies and 18+ years experience make shortlisting highly selective.
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Own and lead end-to-end Subsystem Design Verification (DV) execution and sign-off, including test plan creation, testbench architecture, and milestone reviews.
Define and drive improvements in DV processes to enhance efficiency and quality of verification efforts.
Collaborate cross-functionally with IP, Subsystem, SoC teams, Silicon bring-up, Firmware, and Program Management for DV execution, post-silicon validation support, and root cause analysis of simulation failures.
Master's or Bachelor's degree.
18+ years of relevant design verification experience.
Experience leading core technical project deliveries in design verification at the Subsystem level.
Proficiency in UVM for testbench coding, including BFMs, scoreboards, monitors; proficient in debugging tests using UVM and C; familiar with ARM architecture, AMBA bus standards (AXI-4, CHI, ACE), and interfaces such as DDR, HBM, PCIe, Ethernet, USB.
Seasoned technical leader with experience driving complex Subsystem-level DV projects and coordinating multidisciplinary teams.
Strong coder and architect in UVM and C for simulation testbenches with practical knowledge of industry-standard verification tools (Cadence, Synopsys, Mentor, ARM).
Experienced in collaborating with design, Silicon bring-up, firmware teams, and cross-functional stakeholders in large-scale semiconductor engineering environments.