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Medium; strong employer brand and metro location but highly specialized senior role reduces applicant pool.
High due to niche hardware verification, UVM expertise, and subsystem-level DV specialization.
High; explicit 18+ years and specialized verification tools, interfaces, and subsystem sign-off required.
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Lead and improve design verification (DV) processes for ultra-dense, high-performance SRAM memory compilers within Central Engineering.
Coordinate and drive DV execution across IP, Subsystem, and SoC levels including test plan creation, testbench architecture, debug, coverage closure, and gate-level simulations.
Collaborate with cross-functional teams including Architecture, Silicon bring-up, Firmware, Emulation, and Program Management to support post-silicon validation and subsystem-level DV sign-off.
Master's or Bachelor's degree in relevant field with 18+ years of relevant design verification experience.
Proven experience leading end-to-end Subsystem DV execution and sign-off for complex SoC components.
Proficiency in UVM subsystem/block level testbenches and programming in UVM, C, Tcl, and Perl.
Knowledge of ARM architecture, AMBA bus protocols (AXI-4, CHI, ACE), industry-standard interfaces (DDR, HBM, PCIe, Ethernet, USB), and usage of Cadence, Synopsys, Mentor, and/or ARM verification tools.
Technical leader with deep expertise in subsystem-level design verification and coordination across IP, subsystem, and SoC teams.
Experienced working in silicon and memory compiler IP environments serving large chip companies and big tech clients.
Capable of driving cross-functional collaboration for DV execution and post-silicon validation in complex, high-performance semiconductor projects.