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Tier-1 employer and metro location increase candidate competition despite niche hardware verification skillset.
Hardware RTL and protocol verification skills are highly domain-specific and not easily transferable.
Mandatory RTL/SystemVerilog, protocol experience and EDA tool expertise enforce strict technical shortlisting.
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Develop Formal Verification IPs including Verilog design models and System Verilog Assertions for industry standard bus protocols.
Individually contribute to creation and automation of Assertion Based Verification IPs, coordinating with cross-geographic teams.
Apply strong RTL design, synthesis, and verification concepts including test plan creation and coverage addition, and use EDA tools for debugging design/verification issues.
2+ years of experience in RTL design/Verification for candidates with BE/BTech; Master's degree with internship also acceptable.
Proficient knowledge of at least one industry standard protocol (e.g., AHB, AXI, CHI, PCIe).
Degree in Electrical/Electronics Engineering (BE/BTech/ME/MS/MTech).
Familiarity with scripting languages (Python/TCL) and verification methodologies; formal verification knowledge is a plus but not mandatory.
Operates as an individual contributor with ability to coordinate across geographical teams and disciplines.
Experienced with strong debugging skills and ability to prioritize critical issues.
Comfortable in roles requiring detailed specification understanding, test planning, and using EDA tools (especially Cadence) for verification and debugging.