Back
Tier-1 employer and metro location increase applicants; seniority and niche ATE skills reduce competition.
Highly specialized semiconductor ATE and analog characterization skills limit cross-industry transferability.
Mandatory 10+ years and specific ATE tool, protocol, and scripting experience enforce strict filtering.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Lead test plan generation, test program and hardware development for Power/Analog SoCs from concept through volume production.
Analyze silicon test results, perform failure analysis, and drive yield improvement and test time optimization.
Define and implement test strategy focusing on robust, cost-effective solutions ensuring product quality in collaboration with design and production teams.
Minimum 10+ years experience as a Test Engineer in hardware/software development at Wafer Sort and Final Test for PMIC, Temp Sensors, and I3C products.
Experience with analog ATE platforms such as mFLEX, Advantest 93K, SPEA, Cohu DiamondX (preferred), Teradyne Eagle, or equivalent.
Technical knowledge of electronic devices, analog test techniques, I2C, I3C, SPI protocols, and strong data analysis skills using tools like Spotfire or dataPower.
Work Experience Required: 10+ years in semiconductor test engineering focused on Power/Analog devices.
Experienced with cross-functional collaboration across design, systems, production, and OSAT test offload for complex semiconductor products.
Demonstrates expertise in test strategy formulation, statistical yield analysis, and failure diagnosis in an analog/mixed-signal environment.
Proficient in programming/scripting (C++, Python, C#) and test automation tools (Labview, Teststand) with strong analytical and problem-solving skills.