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Tier-1 employer and Pune metro increase competition despite niche, senior SoC verification skillset.
Highly specialized SoC verification skills limit cross-industry portability.
Strict 8+ years plus mandatory UVM/SystemVerilog, SoC verification, UPF, and SVA experience.
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Architect, enhance, and maintain advanced UVM- and C-based verification environments for in-vehicle networking SoC RTL functional and power-aware verification.
Define and execute comprehensive verification strategies and test plans, driving verification metric closure from IP level to SoC, including directed, constrained random, and formal methods.
Collaborate cross-functionally with Design, Architecture, Validation, and Firmware teams to ensure adherence to automotive quality and verification processes.
8+ years of ASIC/SoC verification experience with track record of multiple chips from specification to tape out.
Expertise in UVM and/or System Verilog-based verification including testbench creation, code and functional coverage, and directed/constrained random stimulus generation.
Experience with low power verification flows (UPF/CPF), SVA assertions, and scripting in C/C++, Perl, Python.
Bachelor's or Master's degree in Electrical or Computer Engineering or related field.
Deep hands-on experience architecting verification environments and driving full closure of verification metrics for automotive SoCs.
Strong familiarity with industry-standard verification methodologies (UVM, SystemVerilog) and low power verification practices aligning with automotive requirements.
Proven ability to work closely with multidisciplinary teams (design, architecture, validation, firmware) in complex SoC development environments.