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Tier-1 brand plus metro location but specialized verification skills yield medium competition.
ASIC/SoC verification expertise is highly domain-specific and not easily transferable across industries.
Explicit senior years requirement and mandatory SystemVerilog/UVM/SoC skills make filtering stringent.
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Contribute to design verification of complex CPU sub-systems and full SoC chips within 5G platforms.
Develop verification environments, test benches, test plans, and coverage plans from scratch for complex ASIC projects.
Execute verification using SystemVerilog, UVM, constrained-random stimulus, and functional coverage while performing debugging with tools like Verdi and Incisive.
Bachelor’s degree in Computer Science, Electrical Engineering, or related fields; Master’s/PhD with 6+ years is also acceptable.
8-12 years of professional experience in ASIC design verification or 6+ years with advanced degree.
Hands-on experience with SystemVerilog, UVM, constrained-random stimulus, functional coverage, and debugging tools (Verdi, Incisive).
Knowledge of AMBA protocols (AXI, AHB, APB) and digital SoC-level verification; experience creating test benches and plans from scratch.
Experienced in ASIC verification lifecycle from environment setup to test development and coverage closure for complex CPU/SoC projects.
Strong understanding of processor architecture, including ARM CPU sub-systems and interrupt controllers.
Detail-oriented with proven ability to independently build verification infrastructure and debug complex digital designs using industry-standard tools.