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Tier-1 brand and Bengaluru metro increase applicant density despite niche, senior ASIC verification requirements.
Specialized ASIC/SoC verification skills and SystemVerilog/UVM expertise limit cross-industry transferability.
Explicit seniority bands and mandatory ASIC verification, SystemVerilog/UVM, and AMBA experience create strict filters.
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Lead design verification for complex CPU subsystems within SoC multi-core ARM CPU processors and radio access SoCs.
Develop and own test benches, test plans, coverage plans, and verification criteria for IP/sub-systems.
Mentor and guide a team of design verification engineers and maintain verification methodologies and flows.
Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 12-17 years experience, OR Master’s/PhD with 5-10 years experience.
Mandatory experience with processors and SoC architectures including ARM CPU subsystems and interrupt controllers.
Hands-on expertise in digital design verification, SystemVerilog, UVM, constrained-random stimulus, functional coverage, and debug tools like Verdi and Incisive.
Experience with AMBA protocols (AXI, AHB, APB) and proficiency in creating verification environments and plans from scratch.
Experienced in ASIC and SoC verification with a strong operational understanding of interrupt controllers and ARM CPU subsystems.
Comfortable leading and mentoring engineering teams on verification strategy and execution in complex CPU subsystem projects.
Proficient in full verification flow ownership: environment setup, test plan development, functional coverage, and debugging with formal verification tools.