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Senior niche SoC verification role with high experience reduces applicant density despite Renesas's strong brand.
Specialized semiconductor verification skills limit cross-industry transferability.
Explicit 15+ years, mandatory UVM and hardware verification tools create rigid screening filters.
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Lead verification of power-efficient IPs, Chiplets, and Chips ensuring functional and performance targets are met.
Manage verification team and processes including test-plan development, reviews, and execution to deliver quality within timelines.
Collaborate with cross-functional teams for specification review, design correctness proof, post-silicon debug support, and verification improvements.
BTech/MTech in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
15+ years of hardware design/verification experience with at least 10+ years in UVM and constrained random verification.
Experience with Cadence Xcelium, eManager+vManager, Verilog, VHDL, System-Verilog and knowledge of functional, ABV, formal verification methodologies.
Experience in verification of Microcontroller and Microprocessor chips, Interconnect, Peripherals including functional, performance and UPF based low power verification.
Senior-level verification engineer with strong expertise in UVM testbench setup from specifications to verification reports and ability to drive independent verification solutions.
Experienced in complex SoC designs involving power management, clocking, system modes, security, and debug domains with protocol knowledge including AHB/AXI/CHI and memory subsystems.
Strategic collaborator able to interface across design, validation, DFT, physical design, and emulation teams to achieve project goals and innovate verification methodologies.