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Tier-1 brand and Bangalore raise competition, but niche senior DDR-PHY specialization limits candidate pool.
Very domain-specific SoC and DDR-PHY verification skills make cross-industry transferability low.
Explicit 12-15 years plus mandatory SystemVerilog/UVM and DDR-PHY expertise make filters highly strict.
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Lead design verification efforts for DDR PHY IP used in next-generation SoCs for devices like smartphones and laptops.
Own the DV testbench, including checkers, scoreboards, assertions, and coverage, ensuring quality sign-off and thorough documentation.
Collaborate with design, subsystem, SoC, SVE teams for failure debug, coverage closure, and resolve silicon-level issues post-silicon.
12 to 15 years experience in design verification of complex IPs, specifically DDRPHY.
Proficiency in Verilog/SystemVerilog and UVM/OVM methodologies, with experience in functional verification and coverage.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with minimum 6 years hardware engineering experience; Master's with 5 years or PhD with 4 years also acceptable.
Knowledge of DDRPHY architecture, DFI protocol, and Jedec standards for latest generations.
Experienced in IP and subsystem level verification with strong debugging and problem-solving capabilities.
Familiar with development of monitors, scoreboards, and sequencers for complex scenario creation using UVM methodologies.
Ability to work cross-functionally across design, subsystem, and silicon validation engineering teams with focus on quality and reliability.