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Tier-1 brand and Bangalore metro increase competition, but niche SystemVerilog/UVM verification limits applicant density.
Hardware IP verification skills are specialized to semiconductor and embedded domains, limiting cross-industry transferability.
Explicit SV/UVM expertise, coverage closure, RTL debug, formal/GLS exposure and degree requirements enforce strict filters.
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Lead end-to-end IP-level verification for wireless IPs including WAN, WLAN, GNSS, and Bluetooth technologies.
Design and execute verification plans using SystemVerilog/UVM, including testbench development, assertion writing, simulation runs, and coverage achievement.
Collaborate cross-functionally for design integration, maintain scalable verification environments, and implement advanced verification techniques to improve efficiency and quality.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years experience; OR Master's degree with 2+ years experience; OR PhD with 1+ year experience in Hardware Engineering or related.
Strong expertise in SystemVerilog/UVM and coverage-driven verification methodologies.
Experience building and maintaining medium-to-complex verification environments and using debugging tools like Verdi.
Location: Bangalore.
Experienced in verification of wireless IPs such as Wi-Fi, Modem PHY, or DSP blocks.
Skilled in advanced DV methodologies including formal/static verification and power-aware verification techniques.
Proficient in scripting languages like Python or Perl for automation within a collaborative, multi-disciplinary hardware engineering environment.