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Tier-1 employer, mid-level experience band, and Bangalore location increase applicant density.
Highly specialized VLSI verification skills limit cross-industry transferability.
Explicit years plus mandatory SV/UVM, HDL, and tool proficiency create strict candidate filters.
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Own design verification of one or more features in the Low Power Audio Subsystem (LPASS) core focusing on ensuring silicon quality at Tape Out.
Develop robust, optimized SystemVerilog/UVM testbenches tailored for specific features or designs under test (DUT).
Implement and explore innovative verification methodologies including formal, simulation, and emulation to enhance testbench quality and efficiency.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with minimum 3 years experience; or Master's with 2+ years; or PhD with 1+ year experience in Hardware Engineering or related.
1-2 years of VLSI industry experience explicitly required.
Strong knowledge of HDLs (Verilog, System Verilog) and proficiency in SV/UVM testbench development.
Proficiency in RTL/TB debugging tools (Verdi or similar) and scripting languages such as Perl or Python.
Experienced in low power audio subsystem hardware verification or related VLSI functional verification environments.
Skilled at owning end-to-end design verification tasks including testbench development and debugging complex RTL/TB issues.
Comfortable applying advanced DV methodologies and tools to improve verification quality and efficiency.