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Tier-1 employer, metro location, and a mid-level AI engineering title increase applicant competition despite niche VLSI specialization.
Role requires deep VLSI RTL and agentic AI expertise, limiting cross-industry transferability.
Explicit years requirement plus required VLSI and agentic AI skills enforce strict candidate filtering.
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Develop AI-driven tools and agentic workflows to optimize and automate RTL front-end design and implementation flows, reducing manual effort.
Build and maintain Python-based automation integrated with existing design tools and engineering workflows focused on RTL to GDS tasks.
Quickly adopt new AI frameworks and open-source tooling to enhance RTL flow execution including analysis, checks, and synthesis steps.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years hardware engineering or related experience, or Master's with 5+ years, or PhD with 4+ years.
Strong hands-on experience with Python scripting and automation including writing and reviewing code.
Basic understanding of VLSI RTL to GDS flow and common front-end stages like RTL checks, synthesis, STA, CDC, formal, DV.
Practical familiarity with agentic AI frameworks and tooling such as LangChain, CrewAI, LangGraph, or similar open-source stacks.
Experienced in developing automation tools within hardware design flows targeting RTL and front-end stages, comfortable with Python and software engineering best practices.
Familiar with current AI-driven agentic frameworks and able to leverage them effectively in a hardware engineering context.
Capable of rapid independent iteration on complex workflows with a strong technical understanding of both RTL hardware design and AI/machine learning tool ecosystems.