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Tier-1 brand and Bangalore increase applicants, but mixed-signal verification niche limits direct competition.
Role requires specialized mixed-signal verification skills and protocol knowledge, limiting cross-industry transferability.
Multiple mandatory technical requirements and explicit experience ranges make shortlisting highly selective.
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Own functional verification for mixed signal logic components including analog behavioral modeling to ensure design compliance.
Develop and execute comprehensive IP verification plans, test benches, and environments covering microarchitecture specifications.
Lead debugging of failing tests in presilicon environments and collaborate with cross-functional teams to refine architecture and verification methodologies.
Bachelor's or Master’s degree in Electronics, VLSI Engineering, or related field.
4-12 years experience for Bachelor’s or 3-10 years for Master’s in ASIC or SoC verification.
Strong expertise in System Verilog, UVM, Verilog, and knowledge of DDR4/DDR5/LP5/LP6 protocols.
Hands-on experience with EDA tools (Synopsys VCS, Cadence Xcelium/JasperGold, Mentor Questa) and scripting in Python, Perl, or Tcl.
Experienced verifier in mixed signal ASIC/SoC environments with skills in constraint-random testing and root cause analysis.
Capable of leading technical reviews and collaborating across digital, analog, RTL, and physical design teams.
Familiar with multi-clock domain mixed signal designs, relevant standard protocols (JTAG, IJTAG, CRI, APB), and advancing verification practices.