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Tier-1 brand and Pune metro increase applicants, but highly specialized senior silicon-validation skills limit competition.
Highly domain-specific semiconductor validation expertise limits cross-industry transferability.
Requires 12+ years, domain-specific silicon validation skills, and leadership, so hiring filters are highly stringent.
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Define and execute validation plans for MCU/MPU subsystems including CPU, memory, peripherals, and interconnects.
Lead silicon post-silicon and pre-silicon validation on platforms, boards, and emulators, including debugging across hardware-software boundaries.
Develop automated test suites and frameworks using C/C++, Python, and scripting; perform low-level hardware and firmware debugging with JTAG, logic analyzers, and trace tools.
Bachelor’s or Master’s degree in Electrical/Electronics/Computer Engineering or related field.
Minimum 12 years of experience in semiconductor validation (analog), product engineering, or silicon debug.
Strong hands-on expertise with MCU architectures, embedded systems, lab bring-up, silicon debug tools (JTAG, logic analyzers, oscilloscopes).
Proven leadership experience managing large, distributed engineering teams.
Experienced in leading complex validation efforts integrating hardware and software teams to close coverage gaps and resolve silicon issues.
Proficient in low-level debugging across CPU cores (ARM/RISC-V), memory subsystems, and common peripherals (UART, SPI, I2C, GPIO).
Able to translate architectural/design specifications into comprehensive validation and automation strategies for silicon platforms.