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Specialized semiconductor CAD role reduces applicant density despite Marvell brand and Bangalore location.
Highly domain-specific semiconductor CAD skills limit transferability across industries.
Explicit 6–10 years, mandatory EDA tools, UPF, and scripting makes screening strict.
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Develop, maintain and enhance PrimeTime-STA & PrimePower-based power signoff and timing analysis flows within Marvell's CAD platform.
Enable and support timing and power-aware optimization during physical implementation collaborating with Physical Design and Front-End teams.
Automate timing & power flow execution and reporting; support tapeout activities ensuring power & timing signoff closure across ASIC projects.
B.E./B.Tech or M.E./M.Tech in Electrical, Electronics, Computer Science or related field.
6 to 10 years of hands-on experience in CAD flow development or power analysis in semiconductor industry.
Proven experience with Synopsys PrimeTime & PrimePower for timing and power analysis.
Proficiency in Tcl scripting and familiarity with FSDB/VCD/SAIF file generation, UPF/CPF power intent and multi-voltage design methods.
Strong expertise in timing analysis flows including hierarchical designs and advanced node timing variations.
Experience collaborating cross-functionally with Physical Design and Front-End teams for timing and power signoff.
Ability to interface with EDA vendors and improve CAD tools through feature evaluation and bug reporting.