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Tier-1 employer, metro location, and mid-level experience increase applicants, but niche DFT skills limit pool.
Highly specialized semiconductor DFT skills not easily transferable across industries.
Explicit 4–8 years plus required DFT tools, MBIST/ATPG and scripting/HDL skills.
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Define and optimize DFT architecture for SoCs including SCAN, MBIST, JTAG boundary scan with focus on high test coverage and performance.
Drive implementation of scan and MBIST insertion flows, timing constraints, ATPG flow, fault model-based test patterns, and pattern simulation for both block and top-level hierarchical scan.
Lead post-silicon bring-up and support activities including pattern validation on ATE, failure analysis, test cost and yield improvement, and mentor junior team members on flow and methodology.
4-8 years of industry experience specifically in DFT domain with experience in bringing at least one or two products to production from architecture through implementation and post-silicon phases.
Hands-on experience with post-silicon activities and preferably with Tessent DFT tools (SCAN, MBIST, LBIST, OCC, EDT, SSN, Boundary Scan).
Proficiency in scripting languages such as Perl, Python, or TCL and good command over HDLs.
Not explicitly mentioned: Educational qualifications and explicit notice period; experience with timing closure and physical design tools like Cadence Genus and Tempus is preferred but not mandatory.
Experienced in hierarchical scan architecture and implementation with a track record of successful DFT deployment across multiple products.
Capable of cross-functional collaboration with product development and CAD tool teams globally, with strong communication and mentoring skills.
Familiarity with low power implementation techniques (UPF/CPF), deep submicron effects, and timing closure viewed as strong advantages for strategic fit.