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Tier-1 brand, Bangalore metro location, and mid-level (3+ years) hiring increase competition.
Specialized mixed-signal verification and EDA tool expertise limits cross-industry transferability.
Explicit 3+ years plus mandatory SystemVerilog/UVM and EDA tool skills create strict screening.
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Perform functional verification of mixed signal logic components, including analog behavioral modeling, ensuring design specification compliance.
Develop and execute comprehensive IP verification plans, test benches, and simulation models for mixed signal microarchitectures.
Lead root cause analysis of design bugs and collaborate with cross-functional teams to optimize architectural features and verification methodologies.
Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, or related field.
3+ years relevant experience with Bachelor's degree or 2+ years with Master's degree in mixed signal verification.
Proficiency in System Verilog, UVM, Verilog and experience with EDA tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa.
Strong scripting skills in Python, Perl, or Tcl and familiarity with standard protocols (JTAG, IJTAG, CRI, APB) and multi-clock domain designs.
Experienced in complex mixed signal IP verification including constraint-random test generation and root cause debugging.
Skilled in collaborating with architects, RTL developers, and physical design teams, handling both digital and analog domains.
Adaptable to hybrid work environment with ability to lead technical reviews and maintain verification infrastructure aligned to industry standards.