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Tier-1 brand and metro location increase competition, but niche DV skills limit applicant pool.
Specialized SoC/IP verification skills severely limit transferability across industries.
Requires specialized UVM/SystemVerilog/IP verification skills and explicit years, so strict filtering.
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Own and develop verification test benches and related verification components for next-generation Infrastructure IPs such as DDRSS and Memory Controllers.
Plan and implement IP/Cluster/Formal verification flows, ensuring coverage closure and quality sign off including documentation.
Collaborate closely with System Architects, Design, Emulation, SoC teams, and cross-functional groups for debugging, root cause analysis, and performance modeling.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field with 4+ years of Hardware Engineering or related work experience; alternatively, Master's degree with 3+ years or PhD with 2+ years.
Experience in IP verification or related, specifically with UVM-based verification methodologies.
Knowledge of ARM bus protocols, virtual memory concepts, and SoC system architecture.
Work Experience Required: 3+ years in IP verification or related role.
Experienced verification engineer with strong expertise in UVM and ARM bus protocols for complex SoC Infrastructure IPs.
Detail-oriented and analytical professional skilled at debugging, functional coverage closure, and post-silicon bring-up coordination.
Capable of working effectively with large, global design organizations and interfacing with multiple teams including system architects and software.