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Tier-1 brand and metro location increase applicants, but niche SoC/UVM specialization moderates competition.
Highly specialized SoC verification skills (UVM/SystemVerilog, RTL, gate-level) limit cross-industry transferability.
Explicit years plus mandatory UVM/SystemVerilog, SoC/IP verification and EDA tool experience create strict filters.
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Develop and own SoC-level and IP-level design verification suites achieving coverage goals according to product specs and verification requirements.
Execute and debug UVM-based verification environments, including simulations (RTL, gate-level, power-aware) and run regressions to achieve DV closure on diverse IPs and subsystems.
Collaborate to improve verification flows and mentor junior engineers ensuring issue resolution and sign-off in a fast-paced development setting.
5-12 years of experience in SoC/IP design verification with participation in successful SoC tape-outs.
Strong expertise in ARM-based microcontrollers and SoC-level verification including C-based DV.
Proficiency in Verilog, SystemVerilog, UVM, constrained-random verification, and familiarity with EDA tools like Synopsys VCS and Cadence Xcelium.
Bachelor's or Master’s degree in Microelectronics, Electronics, or Electrical Engineering.
Experienced in complex SoC design verification environments with a focus on ARM microcontrollers and multiple interface protocols.
Technically hands-on with UVM verification methodology and comfortable working across RTL, gate-level, power-aware simulations, and emulation platforms.
Capable of leading verification closure efforts independently while guiding junior team members and collaborating cross-functionally.