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Tier-1 semiconductor brand but specialized SoC DV skills reduce applicant density.
Deep SoC/UVM/SystemVerilog experience required, making cross-industry transfer difficult.
Explicit 6+ years, mandatory UVM/SystemVerilog and EDA tool expertise increases screening rigidity.
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Develop, own, and execute SoC and IP-level verification suites with coverage targets for complex SoCs.
Design, develop, debug, and run UVM-based verification environments and test cases including RTL, power-aware RTL, gate-level simulation, FPGA and emulation platforms.
Drive design verification closure across diverse IPs and subsystems while mentoring junior engineers and collaborating with design teams for sign-off.
5-12 years of experience in SoC/IP verification with involvement in successful SoC tape-outs.
Strong technical skills in ARM-based microcontroller and SoC-level verification using C-based design verification methodologies.
Proficiency in Verilog, SystemVerilog, UVM, constrained-random verification, and working knowledge of assertions (SVA) and functional coverage.
Experience with EDA tools like Synopsys VCS and Cadence Xcelium; familiarity with low-power verification (UPF) and gate-level/power-aware simulations is a plus.
Experienced in both SoC-level and IP-level verification environments with a hands-on technical approach.
Demonstrates operational ownership by leading DV closure and improving verification reuse and efficiency.
Technical versatility across multiple interfaces (SPI, I2C, UART, USB, PCIe, Ethernet, CAN, eSPI) and familiarity with security Flash IPs and Analog IPs in microcontroller design.