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Tier-1 employer and metro location but senior, niche UVM/SystemVerilog skills limit general applicant pool.
High because specialized SystemVerilog/UVM NAND verification skills have low cross-industry transferability.
Explicit 7–15 years plus mandatory UVM/SystemVerilog and NAND verification make filtering strict.
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Lead full-chip functional verification for non-volatile memory design projects utilizing System Verilog and UVM methodologies.
Develop and execute comprehensive verification plans including test benches, assertions, coverage-driven testing, and behavioral NAND Flash models.
Collaborate closely with digital design and application engineering teams to ensure functional accuracy and drive verification methodology improvements including leveraging AI-assisted tools.
MS or BS degree in Electrical or Computer Engineering or equivalent.
7-15 years of experience in verification collateral development using Verilog, System Verilog, and UVM.
Proficiency in UVM with demonstrated ability to build complex coverage-driven random constraint UVM environments from scratch.
Strong knowledge of digital logic design, circuit design, Verilog RTL coding, System Verilog OOP, and programming languages such as C++, TCL, and PERL.
Experienced in developing and managing complex, full-chip verification environments for non-volatile memory designs.
Skilled in coverage-driven verification methodologies and comfortable utilizing AI-assisted coding and automation tools to enhance verification workflows.
Able to collaborate effectively across design, application, and verification teams within a technology-driven and fast-evolving semiconductor development environment.