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Tier-1 brand and Pune metro attract applicants, but niche SoC verification skills limit broad competition.
Highly specialized SoC/IP verification skills make cross-industry transfers difficult.
Explicit 6+ years plus mandatory UVM/SystemVerilog and SoC/IP verification skills enforce strict shortlisting.
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Develop and own verification suites and execute verification plans for SoC/IP level according to product specifications to ensure coverage and quality goals.
Develop, debug, and run UVM-based verification environments, including test case definition, stimulus creation, running simulations, debugging, and regression analysis across RTL, gate-level, FPGA, and emulation platforms.
Drive verification closure for diverse IPs and subsystems, collaborate with teams to improve verification flow efficiency, and mentor junior engineers.
5-12 years of experience in SoC/IP verification with participation in successful SoC tape-outs.
Strong expertise in ARM-based microcontrollers, SoC-level verification, UVM, SystemVerilog, Verilog, constrained-random verification, and C based DV.
Proficiency with EDA tools such as Synopsys VCS and Cadence Xcelium.
Bachelor’s or Master’s degree in Microelectronics, Electronics, or Electrical Engineering.
Experienced in executing complex SoC verification projects involving multiple interfaces (SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI) and security IPs.
Comfortable working hands-on with low-power verification (UPF), gate-level, and power-aware simulations, aiming for thorough coverage and efficient verification closures.
Proven capability to lead verification teams, mentor juniors, and collaborate closely with design teams for issue resolution and product sign-off.