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Tier-1 brand and metro location increase competition, while niche SoC verification skills limit the pool.
Highly specialized UVM/SystemVerilog and RTL verification skills limit cross-industry transferability.
Explicit 5-12 years plus mandatory UVM/SystemVerilog and SoC verification skills enforces strict shortlisting.
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Own development and execution of SoC and IP-level verification suites to meet coverage goals and product specifications.
Develop, debug, and run UVM-based verification environments across RTL, gate-level, power-aware simulations, and emulation platforms.
Drive design verification (DV) closure on diverse IPs/subsystems ensuring maximum coverage and quality; mentor junior engineers and collaborate with design teams for issue resolution and sign-off.
5-12 years experience in SoC/IP verification with participation in successful SoC tape-outs.
Strong expertise in ARM-based microcontrollers, SoC-level verification, and C-based design verification (DV).
Proficient in Verilog, SystemVerilog, UVM, constrained-random verification; familiar with EDA tools like Synopsys VCS and Cadence Xcelium.
Bachelor’s or Master’s degree in Microelectronics, Electronics, or Electrical Engineering.
Experienced engineer comfortable managing complex SoC/IP verification projects in fast-paced environments.
Strong technical leadership demonstrated by ownership of verification environments and mentoring junior team members.
Hands-on with comprehensive verification methodologies spanning RTL to emulation and coverage-driven verification, especially on ARM microcontrollers and standard interfaces.