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Tier-1 semiconductor brand and metro location increase competition, while niche SoC DV skills moderate applicant density.
SoC verification expertise is highly domain-specific and not easily transferable across industries.
Explicit 6+ years and mandatory UVM/SystemVerilog and SoC verification skills enforce strict filtering.
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Own and develop SoC-level and/or IP-level verification suites using UVM framework to meet coverage goals and verification plans.
Execute complex verification tasks including developing stimulus, assertions, running simulations (RTL, gate-level, power-aware), and regression to ensure design quality.
Drive design verification closure across diverse IPs and subsystems, collaborate with design teams for issue resolution, and mentor junior engineers.
5-12 years experience in SoC/IP verification with successful participation in SoC tape-outs.
Strong expertise in ARM-based microcontrollers and SoC-level verification with C based design verification.
Proficiency in Verilog, SystemVerilog, UVM, constrained-random verification, and familiarity with EDA tools like Synopsys VCS or Cadence Xcelium.
Bachelor’s or Master’s degree in Microelectronics, Electronics, or Electrical Engineering.
Experience working hands-on in fast-paced environments with strong technical delivery capabilities.
Skilled in low-power verification techniques (UPF) and knowledge of multiple interface protocols (SPI, I2C, UART, USB, PCIe, Ethernet, CAN, eSPI).
Demonstrated ability to collaborate cross-functionally and lead junior engineers in complex SoC/IP design verification projects.