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Tier-1 employer but highly specialized SoC DV skills and seniority limit broad applicant competition.
SoC/IP verification skills are highly domain-specific and not easily transferable across industries.
Explicit 10+ years requirement plus mandatory SystemVerilog/UVM/EDA tool and UPF expertise raises screening strictness.
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Lead verification strategy and methodology definition for SoC-level and IP-level, ensuring coverage and quality alignment with product specifications.
Hands-on execution of verification plans including developing and debugging UVM-based environments, creating test cases, running simulations (RTL, power-aware, gate-level, FPGA, emulation), and driving DV closure across multiple IPs.
Mentor team members, collaborate with design teams for issue resolution and sign-off, and ensure compliance with functional safety and security requirements.
10+ years of SoC/IP verification experience with multiple successful SoC tape-outs.
Strong proficiency in ARM-based microcontrollers and SoC-level verification.
Expert in SystemVerilog, UVM, constrained-random verification, and EDA tools such as Synopsys VCS, Cadence Xcelium, Mentor Questa; experience with low-power verification (UPF), gate-level simulations, and functional coverage.
Bachelor’s or Master’s degree in Microelectronics, Electronics, or Electrical Engineering.
Experienced in verification of diverse interfaces including SPI, I2C, UART, USB, PCIe, Ethernet, and eSPI, with knowledge of Flash memory and security IPs (crypto engines).
Experienced in handling complex SoC environments with an emphasis on ARM-based microcontrollers, low-power design verification, and common Analog IPs (ADC, DAC, PLLs).
Operates effectively in fast-paced technical environments with a focus on leadership and hands-on execution of sophisticated verification strategies.