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Tier-1 employer and metro location but niche FPGA verification skills and seniority reduce applicant density.
FPGA pre-silicon verification experience is highly domain-specific and not broadly transferable.
Explicit 8+ years and mandatory UVM/SystemVerilog, FPGA, and protocol verification create strict filters.
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Own the functional logic verification of FPGA designs, ensuring they meet specification requirements through development and execution of verification plans and testbenches.
Lead the debugging and resolution of pre-silicon test failures collaborating closely with FPGA architects, RTL developers, and physical design teams.
Maintain and improve verification infrastructure and methodologies, including documentation and driving technical reviews for verification strategy and coverage.
8+ years of technical experience in Pre-Silicon Validation/Verification.
Degree in Electrical or Computer Science Engineering or related field (BS, MS, or PhD).
Proficiency with OVM/UVM, System Verilog, and constrained random verification methodologies.
Experience in protocol verification, especially DDR and GPIO, and deep knowledge of verification lifecycle including architecture, planning, execution, and coverage closure.
Experienced lead-level engineer with demonstrated expertise in complex IP/SOC verification and FPGA architecture or prototyping.
Strong capability in developing and improving validation test suites with continuous methodology enhancements.
Effective collaborator with cross-functional teams including system and software engineering for integration testing.