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Tier-1 brand and metro hiring balanced by niche DFT specialization.
Highly specialized semiconductor DFT skills limit cross-industry transferability.
Explicit 7–10 years plus mandatory DFT tooling and domain expertise.
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Own design and implementation of DFT features like scan chains, compression, and BIST to improve testability in complex ICs.
Conduct DFT DRC checks and optimize testability metrics using Cadence/Siemens EDA tools.
Collaborate with design, verification, physical design, and test engineering teams to validate DFT structures and resolve test failures.
7-10 years of hands-on experience in DFT methodologies and techniques.
Bachelor's/Master's degree in Electrical/Electronic Engineering or related field.
Expertise in LBIST, ATPG, DFT DRC, Scan compression, Low power DFT, MBIST, Boundary Scan, Analog DFT, JTAG architecture, and DFT STA constraint development.
Proficiency with Cadence/Siemens DFT EDA tools and scripting languages like Perl, Tcl, and/or Python.
Experienced senior-level DFT engineer capable of leading DFT implementation and verification in ASIC design environment.
Strong collaborator working across RTL design, verification, physical design, and test engineering functions to deliver robust testability solutions.
Proficient in tool-based optimization and scripting automation for DFT processes, reflecting high technical expertise and problem-solving ability.