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Tier-1 employer but niche senior SoC verification role and metro location produce medium competition.
Highly specialized SoC verification skills limit cross-industry transferability.
Explicit 12+ years requirement plus mandatory UVM/SystemVerilog/C/Python and SOC domain imply strict shortlisting.
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Lead and execute SOC level verification plans across multiple domains including CPU, DDR, Multimedia, Interconnects, Security, Peripherals, and Power.
Develop and enhance advanced automated testbenches and verification environments using C, SystemVerilog, UVM, and scripting languages.
Mentor junior engineers and collaborate with design, architecture, and pre/post silicon teams to ensure comprehensive verification to tape-out.
Bachelor's degree in Electrical/Electronics/Computer Engineering or related field (Master's or PhD with reduced experience also accepted).
Minimum 12 years of experience in SOC design verification.
Proficiency in C, SystemVerilog, UVM, and scripting languages such as Python or Perl.
Strong understanding of microarchitecture, SOC integration, and experience with simulation, emulation, and formal verification tools.
Expertise in multiple SOC verification domains with a strong focus on design verification closure and automation.
Experienced in leading large scale verification projects from specification to tape-out in a complex SOC environment.
Able to provide technical leadership and mentorship, collaborating across multiple teams including architecture, design, and silicon validation.