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Tier-1 brand and metro location increase competition, while niche senior security verification reduces applicant density.
Highly specialized hardware security verification skills and cryptographic IP experience limit cross-industry transferability.
Explicit senior years, mandatory hardware security verification experience and specific toolset requirements make screening strict.
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Own and lead verification test benches and collateral development for Security IPs in next-gen SoC designs across multiple product categories.
Develop and execute verification plans including test cases for functional correctness, security robustness, coverage closure, and full-chip integration validation of hardware security IPs.
Collaborate with cross-functional teams for RTL debug, coverage closure, integration, and support post-silicon validation and bug resolution.
8.5 to 12+ years of ASIC/SoC functional verification experience with strong ownership of complex IP or subsystem verification.
Minimum 5+ years hands-on hardware security IP verification experience including cryptographic engines and secure processor verification.
Strong expertise in SystemVerilog, UVM, constrained-random testing, test bench architecture, assertions, coverage-driven verification, and debugging.
Bachelor's/Master's/PhD in Computer Science, Electrical/Electronics Engineering or related field with relevant experience (Bachelor +4 yrs, Master +3 yrs, PhD +2 yrs).
Experienced in verification and debug of security-critical hardware blocks including cryptographic engines, secure boot, key management, and random number generators.
Skilled in developing verification components such as monitors, scoreboards, checkers, assertions with deep knowledge of hardware security primitives and SoC protocols (e.g., AXI, APB).
Ability to work with cross-functional global teams including system architects, RTL designers, firmware, software, and physical design for integration and post-silicon validation.