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Tier-1 brand and Bangalore metro increase competition, but niche mixed-signal verification partially limits applicant pool.
Highly domain-specific mixed-signal IP verification skills limit transferability across industries.
Explicit 5–10 years plus mandatory SystemVerilog/UVM and IP verification skills make filters stringent.
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Own and execute the full functional verification flow for DDR PHY IP including test plan creation, testbench architecture, testbench development, design validation, and micro-architectural implementation verification.
Automate validation tasks, analyze verification results, and debug issues across IP, subsystem, and SoC levels in a pre-silicon environment.
Collaborate with architects, RTL developers, and physical design teams to enhance verification methodologies and meet functional, performance, and power targets.
Bachelor's or Master's degree in relevant field with 5-10 years of industry experience in Design Verification using SystemVerilog and OVM/UVM methodologies.
Experience across the entire validation flow: testbench architecture, test plan creation, verification closure, waveform debug, functional and code coverage, VCS NLP/non-NLP simulations, and gate level simulation (GLS).
Work location: Bangalore, India with hybrid work model eligibility.
Not explicitly mentioned: specific notice period.
Experienced in DDR PHY IP verification and familiar with DFx features.
Proficient in scripting languages such as Python or Perl to automate validation tasks.
Experience with version control tools like Git, familiarity with VSCode, GitHub Copilot or AI-assisted coding tools, indicated for effective collaborative and efficient workflow.