Back
Tier-1 employer and metro location increase applicant density, but niche principal ASIC specialization limits competition.
Highly domain-specific ASIC and SoC architecture skills limit cross-industry transferability.
Explicit 12+ years, mandatory ASIC/SoC architecture and RTL skills make shortlisting highly strict.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Own architecture and micro-architecture for compute, memory, interconnect, and interfaces in AI inference SoCs.
Lead performance, power, and area (PPA) analysis and guide trade-offs across RTL and architecture teams.
Collaborate closely with software and physical design teams to co-optimize hardware features for AI workloads and guide RTL implementation.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
12+ years of experience in SoC design, architecture, RTL design, and micro-architecture.
Strong skills in Verilog/SystemVerilog, C/C++, and scripting languages (Python/Tcl/Perl).
Deep understanding of computer architecture, memory hierarchies, SoC interconnects, and AI/ML compute architectures with proven PPA optimization experience.
Experienced in owning complex SoC blocks or subsystems through full development cycle including silicon delivery.
Demonstrated expertise in AI inference workload optimizations and hardware-software co-design.
Operates at senior architectural level with strong technical influence across multidisciplinary teams (RTL, verification, physical design, software).