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Tier-1 brand and metro location increase competition, but 15+ years and niche analog-EDA skills limit applicants.
Requires deep analog/VLSI and CAD experience, limiting cross-industry transferability.
Mandatory 15+ years, specific analog-EDA and scripting expertise make screening highly selective.
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Develop and implement end-to-end AI workflows for Analog IP creation covering schematic generation, layout, design optimization, simulation, verification, and signoff at advanced FinFET nodes.
Collaborate with Data Science teams throughout all phases to utilize available EDA AI tools for Analog IP design automation.
Architect custom design and verification methodologies for mixed-signal IPs integrating AI/ML techniques where applicable.
15+ years of experience in defining Analog and Digital design methodologies and flows.
Strong proficiency in Python, SVRF, and SKILL scripting for CAD and automation.
B.Tech / M.Tech / MS degree in VLSI Design, Microelectronics, or a related field.
Deep understanding of transistor-level circuit design including device behavior, biasing, matching, noise, and variability.
Experienced in architecting and automating mixed-signal IP design and verification at advanced process nodes using AI/EDA tools.
Operates effectively with multidisciplinary teams involving data science and design automation.
Senior technical leader with proven ability to integrate AI/ML techniques in EDA workflows for analog/mixed-signal design.