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Tier-1 brand and Bangalore location increase applicant density despite niche ASIC verification skillset.
Highly domain-specific ASIC/SoC verification skills limit cross-industry transferability.
Explicit 5–10 years, mandatory SystemVerilog/UVM, SoC tapeout and EDA tool expertise impose stringent filters.
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Own verification of SoCs, automotive ASICs, IPs, and subsystems using Metric-driven and/or Formal Verification methodologies.
Develop and track verification plans and environments from scratch, including creation and integration of Verification-IP (VIP).
Measure and analyze regression results and continuously improve verification methods/tools/flows with EDA partners.
5 to 10 years experience in Digital RTL verification using System Verilog and UVM.
Bachelor or Master degree in Electronics and Communication (BE / B.Tech / ME / M.Tech).
Must have participated in one or more ASIC/SoC tape outs.
Experience with constrained random verification, functional coverage development, and AMBA protocols knowledge.
Experienced in building verification environments from ground up and using UVM/OVM methodologies effectively.
Hands-on with major EDA tools from Cadence, Synopsys, and Mentor.
Familiarity with ARM processor-based subsystem/SoC verification and scripting languages like Perl, TCL.