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Niche PDK/EDA skills lower applicant pool, but metro location and mid-level experience raise competition.
Highly domain-specific semiconductor and EDA skills limit cross-industry transferability.
Requires specific degree, Cadence Virtuoso expertise, PDK experience and SKILL/Python automation, so filters are strict.
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Develop, validate, and release process design kits (PDKs) including device models, pcells, technology files, and DRC/LVS/PEX rule decks for analog and mixed-signal technologies.
Support and enable advanced semiconductor process technologies including GaAs, HBT, and foundry nodes at 22nm and above for analog/RF designs.
Collaborate with foundries, process teams, and design groups to resolve PDK issues; build regression and quality assurance infrastructure with version control and release management.
M.Tech/M.E./M.S. in Electrical Engineering/Computer Engineering or equivalent from a reputed university.
3–5 years experience in PDK development, technology enablement, and CAD/methodology for analog/mixed-signal design.
Hands-on experience with Cadence Virtuoso flows including OA database, pcells, techfile, and rule deck integration.
Strong understanding of semiconductor device physics for analog/RF (MOS, bipolar/HBT), with experience in DRC/LVS/PEX deck development or validation in production PDK environments.
Experienced in supporting GaAs or SiGe HBT PDKs for RF applications such as power amplifiers, LNAs, or switches.
Familiarity with enabling advanced nodes (22nm and above) in analog/RF designs and understanding of RF-specific layout effects and EM-aware PDK considerations.
Comfortable working cross-functionally with foundries and internal teams to drive PDK quality and timely releases in a complex semiconductor environment.