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Tier-1 employer, Bangalore location, and mid-level role increase applicant density despite niche SoC specialization.
Specialized ASIC/SoC verification, RTL, and tape-out expertise limits cross-industry transferability.
Explicit 4+ years requirement plus mandatory ASIC verification, RTL, and tape-out experience makes screening stringent.
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Define and track project milestones for Switch SoC design using agile frameworks.
Develop system-level methodologies, tools, and IPs for scalable SOC build and integration.
Lead SOC assembly, integrate components, and deliver models for verification at multiple levels (cluster, subsystem, SOC, emulation).
Bachelor’s or Master’s degree with 4+ years semiconductor design and architecture experience on complex SoCs.
Experience across all SOC development phases: architecture, micro-architecture, RTL design, verification, timing closure, and physical design.
Proficient in Verilog/SystemVerilog or equivalent, simulation/debug tools, and scripting languages like Perl or Python.
Hands-on experience with multiple successful tape-outs of complex, high-volume SoCs on advanced process nodes.
Experienced in leading complex SOC deliveries for enterprise or HPC applications with chip lead responsibilities.
Strong RTL coding and debugging skills with ability to perform power, performance, and area trade-off analyses.
Collaborative with cross-functional teams including physical design and software to optimize ASICs and define HW/SW interfaces.