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Senior niche VLSI verification role with specific SystemC/SystemVerilog skills reduces applicant density.
Highly specialized VLSI verification skills and NAND/memory knowledge limit cross-industry transferability.
Explicit 13+ years requirement and mandatory SystemC/C++/SV/UVM skills create strict screening filters.
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Develop and code C++ and SystemC models and create associated tests for verification.
Validate developed models using SystemC/SystemVerilog/UVM testbenches and debug issues in the firmware environment.
Mentor junior engineers and collaborate with other teams to identify and resolve root causes of failures.
Minimum 13 years of relevant work experience in functional modeling and verification.
Proven hands-on experience with C++, SystemC, test creation, and C-based testbench development.
Bachelor's or Master's degree in Electronics and Communication or Embedded Systems from a reputed institution.
Experience with Visual Studio, Git, and Bitbucket tools.
Experienced in NAND concepts and knowledge of memory and digital design concepts (SRAM/DRAM/ROM/Flash) preferred.
Proficient in C, C++, Python, SystemC, with additional skills in Verilog/SystemVerilog/UVM considered a plus.
Demonstrated ability in team leadership and mentoring within complex embedded systems verification environments.