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Tier-1 brand and metro location increase competition, but niche ASIC verification skills moderate applicant density.
Highly domain-specific ASIC verification skills and hardware protocols limit cross-industry transferability.
Explicit 4-8 years plus mandatory SystemVerilog/UVM and emulation/Gate-Level requirements enforce strict filtering.
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Develop and execute comprehensive verification test plans for SoC designs using methodologies including RTL simulation, FPGA prototyping, and Palladium emulation.
Lead gate-level and power-aware simulations while debugging complex SoC and subsystem designs to ensure high-quality and reliable controller development.
Collaborate with cross-functional teams to define and implement coverage-driven verification strategies and develop advanced verification environments using UVM and PSS testbenches.
BE or MS degree in Electrical/Electronics Engineering or Computer Engineering.
4-8 years of experience in SoC verification, including UVM methodology and verification environments.
Proficiency in C, SystemVerilog, Verilog, and scripting languages such as Python, Perl, TCL, and BASH.
Knowledge of bus protocols (AXI, AHB, APB), interfaces (PCIe, UART, I2C, SPI, USB, SD), chiplet protocols including UCIe, and experience with gate-level simulations.
Experienced in building and enhancing UVM-based verification methodologies for high-performance SoC controllers.
Hands-on expertise in complex SoC and subsystem verification in processor-based environments (e.g., ARC, ARM, RISC architectures).
Operational strength in cross-team collaboration, debugging, and applying coverage-driven verification in large semiconductor product development.