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Tier-1 brand and metro location increase interest, but niche DV/UVM skills limit broad applicant pools.
Hardware DV skills (UVM, SystemVerilog, silicon debug) are highly specialized and not easily transferable.
Explicit years plus mandatory UVM/SystemVerilog and IP verification experience make filters highly strict.
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Own and develop verification test benches, checkers, trackers, scoreboards, assertions, and functional coverage for next-generation Infrastructure IPs such as DDRSS and Memory Controllers.
Plan and implement IP/Cluster/Formal verification flows, coordinate with Design and SoC teams throughout the IP development cycle, and lead quality sign-off and documentation.
Debug regression failures, perform post-silicon issue root cause analysis collaborating with Design, SW, and test teams; support latency and bandwidth analyses with SoC level performance modeling teams.
Bachelor's degree in Electronics & Communication / Micro Electronics or related field; Master's or PhD accepted with relevant experience.
3+ years of experience in IP verification or related hardware engineering work.
Strong expertise in UVM-based verification and familiarity with ARM bus protocols and SoC system architecture.
Experience developing monitors, scoreboards, sequencers using SystemVerilog, UVM, and scripting languages such as Python or Perl for automation.
Experienced in verification of complex Infrastructure IPs within a large, worldwide semiconductor design organization.
Proficient in debugging and root cause analysis across RTL, verification regressions, and post-silicon silicon bring-up.
Familiar with low power design verification techniques and automotive safety standards (ASIL) is a plus, along with HW-SW debug and performance modeling experience.