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Senior, niche DFT role at a Tier-1 firm in a metro city produces moderate competition density.
Highly specialized semiconductor DFT skills are industry-specific and not easily transferable across industries.
Explicit 12+ years, 10+ years DFT, tool mandates, and export-control eligibility create strict filtering.
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Lead design-for-test (DFT) architecture and implementation for complex ASIC/SoC designs on advanced 3nm, 2nm nodes and beyond.
Own end-to-end DFT execution from RTL insertion through mass production readiness and post-silicon debugging.
Mentor and guide DFT engineering teams while collaborating cross-functionally on physical design, timing closure, and test data optimization.
Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or related field.
12+ years total experience with 10+ years direct DFT experience in custom chip design industry.
Proven experience leading DFT architecture on at least 2 complex designs.
Strong hands-on with Siemens Tessent or Synopsys TestMax for DFT insertion, ATPG, MBIST flows.
Experienced DFT technical leader with comprehensive knowledge of DFT architectures, methodologies, and advanced ASIC SoC tape-outs.
Strong in cross-functional collaboration with physical design, timing closure, and manufacturing teams in high-complexity, multi-die environments.
Customer-facing technical communicator capable of mentoring senior engineers and advancing next-generation DFT methodologies and automation.