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Tier-1 brand and Bangalore location increase applicant density despite niche verification skill requirements.
SoC/ASIC verification skills are specialized and not easily transferable across unrelated industries.
Explicit years, degree, and deep UVM/SystemVerilog and gate-level simulation requirements make screening stringent.
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Develop and execute comprehensive verification test plans for high-performance SoC designs incorporating RTL simulation, FPGA prototyping, Palladium emulation, and gate-level simulations.
Collaborate with design, architecture, and firmware teams to define and implement coverage-driven verification methodologies and advanced verification environments including UVM and PSS testbenches.
Analyze functional coverage and simulation results to enhance verification efficiency and reliability of SoC products in data storage solutions.
Bachelor’s or Master’s degree in Electrical/Electronics Engineering or Computer Engineering.
4-8 years of relevant SoC verification experience with strong proficiency in C, SystemVerilog, UVM, and coverage-driven verification methods.
Experience with bus protocols (AXI, AHB, APB), chiplet protocols including UCIe, and interfaces such as PCIe, DP, UART, I2C, I2S, SPI, USB, SD.
Proficiency in programming/scripting languages like Python, Perl, TCL, and BASH; strong debugging and problem-solving skills.
Experienced in building and improving UVM-based verification methodologies for processor-based SoCs, especially ARC, ARM, RISC architectures.
Hands-on expertise in advanced testbench development including scoreboards and checkers, and setting up gate-level and power-aware simulations.
Able to collaborate cross-functionally with design, architecture, and firmware teams to drive verification strategies and deliver reliable SoC products.