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Tier-1 employer, mid-level experience band, and Bengaluru metro location increase candidate competition.
ASIC/SoC verification requires specialized hardware verification skills, limiting cross-industry transferability.
Explicit 5–8 years plus mandatory SystemVerilog/UVM, SoC verification, GLS and DFX skills create strict filters.
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Develop and execute verification test plans and test cases for SoC designs across RTL simulation, FPGA prototyping, and Palladium emulation platforms.
Perform Gate-Level Simulations (GLS), debugging complex SoC designs, and contribute to coverage-driven verification methodologies using UVM and PSS testbenches.
Collaborate with design, architecture, and firmware teams to define verification strategies and generate functional patterns for post-silicon testing and wafer sorting.
Bachelor's or Master's degree in Electrical/Electronics Engineering or Computer Engineering.
4-8 years of experience in SoC verification, specifically with processor-based SoCs (ARM, RISC-V, ARC).
Strong expertise in C, SystemVerilog, UVM, and coverage-driven verification methodology.
Experience in DFX verification and generating functional patterns for post-silicon testing.
Experienced in developing and improving UVM-based verification methodologies and advanced testbenches including scoreboards and checkers.
Proficient in various bus protocols (AXI, AHB, APB) and interfaces (PCIe, LPDDR, UART, I2C, I2S, SPI).
Skilled in debugging complex SoC designs and capable of collaborating closely with cross-functional teams for verification strategy alignment.