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Tier-1 brand and Bangalore metro increase competition, but senior, niche ASIC DV role reduces applicant density.
Highly specialized ASIC design verification skills limit transferability across industries.
Explicit 15+ years, mandatory verification technologies, and large-team management make hiring filters highly stringent.
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Lead design verification efforts for complex digital IP components and subsystems, from concept through release across product teams.
Manage and mentor a large team (20+ members) of design verification engineers, including planning and executing verification strategies.
Collaborate with multiple business units, design, architecture, and firmware teams to define verification plans and improve verification processes.
Bachelor’s or Master’s degree in Electronic Engineering or related field.
At least 15 years of ASIC design verification experience.
Experience managing teams of 20 or more engineers.
Proficiency in digital verification methodologies and languages including SystemVerilog, Verilog, C/C++, TCL, Perl, Python, with expertise in constrained-random verification, functional and code coverage, assertion-based methodology, and mixed-signal simulators.
Senior-level design verification expert with deep experience leading large teams and defining strategic verification methodologies.
Experience with SoC-level verification including processor-based verification and gate-level simulation flows.
Technical versatility including application of AI tools in verification workflows, familiarity with low-power verification methodologies (CPF, UPF), and scripting for verification automation.