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Tier-1 semiconductor brand and Bangalore location increase competition despite niche UVM/DV specialization.
Hardware design verification skills are highly domain-specific, limiting transferability across industries.
Mandatory 6–10 years DV experience with UVM/formal and SoC expertise makes shortlisting highly strict.
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Own development and architecture of verification environments for complex digital designs using UVM and Formal verification methodologies.
Define test plans, conduct block and sub-system level verification including integration and collaborate with design, analog co-sim, firmware teams for top-level verification.
Evaluate and benchmark third-party IPs for design quality and DV environment integration; support post-silicon verification activities.
Bachelor's degree in Electrical/Electronics/Computer Science (B.E./B.Tech).
6-10 years of experience in design verification using UVM and constrained random, coverage-driven approaches.
Experience with DV concepts including test plan translation into verification environments and coverage metric generation.
Ability to travel up to 10%; knowledge of assertion-based formal verification is required.
Experience with complex digital interfaces and protocols such as DDR, Ethernet, USB, PCIe, MIPI, HDMI, and eMMC/SD.
Strong architectural understanding aimed at scalable DV environment development optimizing first pass verification success.
Familiarity with ASIC/SoC product verification, processor/SoC architecture, and ability to collaborate across globally distributed teams.