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Tier-1 brand but highly specialized senior ASIC DV role limits applicant density.
ASIC design verification skills are highly domain-specific and not easily transferable across industries.
Explicit 15+ years, 20+ reports, and deep DV methodology requirements enforce strict screening.
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Lead design verification of complex digital IP components and subsystems from concept through release, ensuring thorough validation using advanced methodologies.
Manage and mentor a large team (20+ engineers) to plan and execute comprehensive design verification strategies across multiple business units.
Collaborate with design, architecture, firmware, and product teams to define test plans, enable SoC use cases, and drive continuous improvements in verification processes.
Bachelor’s or Master’s degree in Electronic Engineering or related field.
At least 15 years of ASIC design verification experience.
Experience managing teams of 20 or more engineers.
Technical proficiency in digital verification methodologies including constrained-random verification, functional/code coverage, assertion-based and formal verification, and knowledge of relevant tools and languages such as SystemVerilog, Verilog, C/C++, scripting languages, and mixed-signal simulators.
Experienced leader with strong ability to define and implement large-scale verification strategies in semiconductor IP environments.
Demonstrated success in managing sizable, high-performing engineering teams.
Hands-on expertise bridging design verification with software and firmware teams, comfortable working cross-functionally in a matrix organization supporting advanced SoC products.