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Tier-1 Bangalore role but specialized verification skills reduce applicant density.
Highly specialized semiconductor verification skills limit transferability across industries.
Explicit 6–15 years, block ownership and specialized RTL/DFT/timing requirements create strict filters.
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Define and optimize micro-architecture of digital blocks aligned with product goals.
Own block or subsystem design and verification including RTL coding, synthesis, timing constraint development, and integration.
Mentor junior engineers and support silicon validation including debugging and DFT activities.
Degree in Electrical/Electronics/Computer Science (BE/BS/MTech/ME/PhD) from a reputed institute.
6-15 years of relevant experience with at least 3 years in block or subsystem design ownership.
Strong RTL coding skills in Verilog/SystemVerilog, and expertise in digital logic design, timing closure, synthesis, and industry-standard bus protocols (AHB, APB, AXI).
Willingness to travel up to 10%; export licensing review possible for non-US citizens.
Experienced in control-intensive, data-path intensive, and multi-domain clocking design environments with subsystem and chip integration exposure.
Proficient in debugging, silicon validation, DFT, and mentoring junior engineers within a geographically distributed team.
Preferred experience in digital signal processing, Matlab modeling, and processor subsystem design.