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Tier-1 brand presence and Bangalore metro boost competition, balanced by niche senior ASIC verification requirements.
ASIC/SoC verification expertise is highly specialized and not easily transferable across industries.
Explicit 13+ years requirement plus mandatory SystemVerilog/UVM, PCIe, gate-level and power-aware verification skills.
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Own end-to-end verification flows for one or more SoC subsystems including planning, execution, and closure.
Develop and execute verification strategies using UVM/SystemVerilog and C-based tests, ensuring functional and code coverage goals.
Lead debugging across digital logic, firmware, timing, and DFT domains; collaborate with design, validation, and firmware teams for system-level issue resolution.
13+ years of experience in ASIC SoC verification.
Bachelor's or Master's degree in Electrical or Computer Engineering.
Expertise in C programming, SystemVerilog UVM, and coverage-driven verification methodologies.
Experience with bus protocols (AXI, AHB, APB), interfaces (PCIe, LPDDR, I2C, I3C, SPI), and power-aware verification (UPF/CPF).
Proven ability to build and improve reusable verification methodologies and infrastructure across multiple projects.
Strong cross-functional collaboration experience including mentoring junior engineers and working with RTL designers, architects, and firmware teams.
Experienced in gate-level simulations with SDF annotation and regression automation using scripting languages (Python, Perl, TCL).