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Tier-1 brand and metro location increase applicants, but niche DFT skillset limits broad competition.
DFT and ASIC post-silicon skills are highly domain-specific and not easily transferable across industries.
Explicit 4–7 years plus mandatory DFT tools, ATPG, simulation, and scripting makes filtering stringent.
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Implement, verify, and validate Design For Test (DFT) structures on advanced ASIC/SoC designs within Custom Silicon Engineering.
Execute DFT insertion flows, ATPG pattern generation and validation, and DFT design rule checking for assigned IP blocks or SoC partitions using Siemens Tessent or Synopsys TestMax.
Support post-silicon bring-up and debug activities; develop automation scripts and collaborate with Physical Design and timing teams on DFT implementation constraints.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
4–7 years of experience in Design For Test (DFT).
Hands-on experience with Siemens Tessent and/or Synopsys TestMax tools and running DFT flows with simulators like Synopsys VCS or Cadence Xcelium.
Eligibility to access export-controlled technology per U.S. export control laws (EAR).
Experienced in advanced DFT methodologies including scan, MBIST, JTAG/IJTAG, ATPG (SAF/TDF), and compression techniques.
Familiar with Linux environment and scripting languages (Tcl, Perl, Python) for DFT automation tasks.
Capable of technical collaboration across global teams with problem-solving skills focused on DFT insertion, validation, and debug in complex ASIC/SoC projects.