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Strong Tier-1 employer and metro location increase competition, but niche senior DFT skills reduce applicant density.
Highly domain-specific ASIC/DFT expertise limits cross-industry transferability.
Mandatory 8+ years, specialized DFT tools, and post-silicon experience create strict hiring filters.
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Lead DFT implementation including scan insertion, MBIST, IJTAG, ATPG pattern generation, and validation for complex SoC partitions in Custom AI, XPU, and high-performance compute designs.
Execute and optimize DFT flows from RTL to gate-level including DRC, LEC equivalence checking, STA for test modes, and test data volume management.
Develop and maintain DFT automation and methodology, support post-silicon bring-up debugging, collaborate with Physical Design teams, and mentor junior engineers.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
8+ years of hands-on DFT experience including scan insertion, MBIST, JTAG/IJTAG, ATPG, EDT compression, and DFT validation.
Proficiency with Siemens Tessent and/or Synopsys TestMax and RTL/gate-level DFT flows.
Eligibility to access U.S. export-controlled technology; export license review may apply.
Experienced DFT expert recognized within teams for broad execution and some architectural input on complex SoC designs at 7nm or below.
Strong track record in meeting deadlines for DFT deliverables and supporting post-silicon bring-up via scan chain and pattern debugging.
Collaborative communicator able to work effectively in geographically distributed teams and mentor junior engineers.